Skip to main content Jan 2025 - now Jan 2025 - now AMBER Affordable Multimodal Sensor-Based Environmental Risk Detector AI/ML ›
- Engineered a wearable industrial helmet, with 6 multimodal sensors & edge computing to detect environmental hazards
- Developed a custom data pipeline and TLV-based sensor communication protocol in python, optimizing sensor fusion
- Soldered and wired electronic components, ensuring durable sensor connectivity and efficient signal processing
Jun 2024 - now Jun 2024 - now VibraView Haptic obstacle detection wearable for the visually impaired Hardware ›
- Developed a real-time assistive obstacle detection system with haptic feedback for visually impaired users
- Engineered a functional proximity-based prototype with 6 components for less than $15 using Raspberry Pi Pico
Sep 2025 - May 2026 Sep 2025 - May 2026 IMPACT Cap STM32 smart-helmet firmware and data pipeline for environmental and biometric monitoring around self-injurious behavior Hardware ›
- Led embedded application architecture for a 7-task STM32U575 FreeRTOS runtime capturing PDM audio through MDF/GPDMA and generating 5-second telemetry summaries
- Designed portable C impact_core modules for state management, impact detection, time synchronization, Pipeline A/B serialization and retry policy; validated 70 core and 9 DSP tests
- Implemented runtime JWT acquisition and refresh with authenticated ST67 Wi-Fi uploads through a Cloudflare-to-Cloud Run relay; validated 31 consecutive HTTP 201 responses
- Built ThreadX/FileX SD prototype with single-writer queue ownership and drain, flush, close and unmount lifecycle; verified 24 Pipeline A and 24 Pipeline B JSONL records
May 2026 - May 2026 May 2026 - May 2026 IMPACT Band BLE impact-detection wearable built on the Seeed Studio XIAO nRF52840 Sense Hardware ›
- Sampled the onboard LSM6DS3TR-C 6-axis IMU at 104 Hz and aggregated acceleration and detected impacts into 5-second window summaries
- Implemented Nordic UART Service transport for newline-framed JSON plus a Python/Bleak receiver for packet reassembly and JSONL logging
- Built 17 native firmware tests covering packet construction, window aggregation, impact detection and long-packet BLE transport behavior
- Validated physical taps up to 8.989g dynamic acceleration and recovered an intermittently failing battery-prepared board using a replacement control board
Oct 2023 - Dec 2023 Oct 2023 - Dec 2023 BitBlaster 10-bit processor with RAM Hardware ›
- Co-engineered a custom 10-bit processor with a multi-stage ALU capable of executing 14 arithmetic and logic operations
- Authored over 600 lines of System Verilog code and successfully demonstrated the processor on a DE10-Lite FPGA board
Sep 2023 - Dec 2023 Sep 2023 - Dec 2023 FPGA Digital Logic Lab Hardware module portfolio in SystemVerilog for combinational and sequential circuit design. Hardware ›
- Completed 8 SystemVerilog/Verilog HDL labs on DE10-Lite FPGA covering Boolean logic, FSM, ALU, and sequential circuits
- Developed 20+ synthesizable modules: decoders, adders, multipliers, FSMs, debouncers with hierarchical design
- Verified hardware on MAX 10 FPGA using Quartus Prime with synthesis, simulation, pin assignment, and physical testing
Sep 2016 - Mar 2018 Sep 2016 - Mar 2018 President Junior Engineers, Technicians, and Scientists (JETS) club, GAI Leadership ›
- Planned and led school's first science fair with 3 teachers, featuring 38 students building 13 projects
- Student projects included solar generators, electromagnets, LED lamps, backup power packs, and handheld fans
- Built DIY projects including batteries from household chemicals, electromagnetic railgun, and electrolysis unit
- Demonstrated 3 taser models and multiple coiled transformers to science teachers
- Collaborated with teachers to maintain and restock Biology, Physics, and Chemistry labs